1. Field of the Invention
The present invention relates to a circuit and a method for generating an internal clock signal and, more specifically, to a circuit and a method for generating an internal clock signal in a semiconductor memory device, which generates the internal clock signal for synchronizing the operation of the circuit within the semiconductor memory device by using an externally inputted clock signal.
2. Discussion of Related Art
A device that operates in synchronism with a clock signal employs an external clock signal to generate an internal clock signal whose pulse width is constant for the purpose of a stable operation within the circuit.
FIG. 1 is a circuit diagram illustrating a circuit for generating an internal clock signal according to a prior art.
Referring to FIG. 1, the circuit for generating the internal clock signal includes a delay unit 110 and a pulse-shaping unit 120. In the above, the delay unit 110 delays an external clock signal (Ext_CLK) by time corresponding to a desired pulse width. The pulse-shaping unit 120 logically combines a signal (A) that is delayed by given time by the delay unit 110 and the externally inputted clock signal (Ext_CLK) to generate an internal clock signal (Int_CLK) having a target pulse width (for example, pulse width corresponding to delay time performed in the delay unit).
Meanwhile, the pulse-shaping unit 120 includes a first NAND gate N121 for performing a NAND operation for the external clock signal (Ext_CLK) and the delay signal (A) of the delay unit 110, a second NAND gate N122 for performing a NAND operation for the external clock signal (Ext_CLK) and the output signal of the first NAND gate N121, and an inverter I121 for inverting the output signal of the second NAND gate N122. At this time, a NAND gate may be further added between the second NAND gate N122 and the inverter I121.
FIGS. 2A to 2C show internal waveforms for explaining the process of generating the pulse in the circuit for generating the internal clock signal shown in FIG. 1.
FIG. 2A of them shows a waveform where the delay width of the pulse by the delay unit is smaller than that of the external clock signal. Referring to FIG. 2A, in the event that a delay width (DW) between the delay signal (A) delayed by the delay unit and the external clock signal (Ext_CLK) is smaller than a pulse width (PW) of the external clock signal (Ext_CLK), the internal clock signal (Int_CLK) is normally generated by the logical combination of the logical devices included in the pulse-shaping unit (120 in FIG. 1). In other words, the rising edge of the internal clock signal (Int_CLK) is synchronized to the rising edge of the external clock signal (Ext_CLK). Meanwhile, the pulse width of the internal clock signal (Int_CLK) is set to the delay width (DW) between the delay signal (A) delayed by the delay unit and the external clock signal (Ext_CLK). Therefore, the pulse width of the internal clock signal (Int_CLK) can be controlled by adjusting the degree of delay of the delay unit.
Further, FIG. 2B shows a waveform where the delay width of the pulse by the delay unit is coincident with the pulse width of the external clock signal. Referring to FIG. 2B, in case that the delay width (DW) between the delay signal (A) delayed by the delay unit and the external clock signal (Ext_CLK) is coincident with the pulse width (PW) of the external clock signal (Ext_CLK), the internal clock signal (Int_CLK) is normally generated by the logical combination of the logical devices included in the pulse-shaping unit (120 in FIG. 1). In other words, the rising edge of the internal clock signal (Int_CLK) is synchronized to the rising edge of the external clock signal (Ext_CLK). Further, in this case, the pulse width (PW) of the external clock signal (Ext_CLK) is set to the pulse width of the internal clock signal (Int_CLK) as it is.
Meanwhile, in the event that the delay width (DW) between the delay signal (A) delayed by the delay unit and the external clock signal (Ext_CLK) is greater than the pulse width (PW) of the external clock signal (Ext_CLK), a problem may take place.
FIG. 2C shows a waveform, in which the delay width of the pulse by the delay unit is greater than the pulse width of the external clock signal. Referring to FIG. 2B, in case that the delay width (DW) between the delay signal (A) delayed by the delay unit and the external clock signal (Ext_CLK) is greater than the pulse width (PW) of the external clock signal (Ext_CLK), the internal clock signal (Int_CLK) is abnormally generated by the logical combination of the logical devices included in the pulse-shaping unit (120 in FIG. 1). In other words, the rising edge of the internal clock signal (Int_CLK) is not synchronized to the rising edge of the external clock signal (Ext_CLK) and a time point where the internal clock signal (Int_CLK) is enabled according to the frequency of the external clock signal (Ext_CLK) (time point where the rising edge takes place) is differentiated. Further, the pulse width of the internal clock signal (Int_CLK) is set to the width of a High-level portion of the pulse delayed by the delay unit and a portion in which the High level of the external clock signal (Ext_CLK) is not overlapped., The pulse width of the internal clock signal (Int_CLK) can be abruptly reduced depending on the operating frequency (for example, the external clock signal).
As such, if the time point where the internal clock signal is enabled (for example, the rising edge) is changed depending on the frequency of the external clock signal and the pulse width is abruptly reduced, the operating margin within the circuit is reduced to cause malfunction. This degrades reliability of the circuit and may cause fail even worse.